1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique which is effective to prevent a wire from being broken.
2. Description of the Prior Art
In a conventional process of assembling a semiconductor integrated circuit, the following steps have been performed. That is, in an Ag spot plating step, an Ag spot plating is applied to a front end portion (including portions obtained by wire bonding a chip and a lead frame by an Au wire) of a lead of a pressed or etched lead frame (hereinafter referred to as an inner lead) molded by a mold. Next, in a step of assembling a package, a die bonding, a wire bonding and an assembly of the package to be molded are performed In a subsequent outer plating step (including a dipping step), in order to mount to a printed circuit board or a circuit board, a Sn—Pb system solder layer is previously attached to a portion including a contact portion between a lead which is not molded by the mold (hereinafter referred to as an outer lead) and the substrate in accordance with an outer plating. After the Ag spot plating step and the outer plating step mentioned above are finished, the process goes to a step of working a product.
However, in recent years, when a countermeasure to an environmental problem is required, in particular, as is indicated in Japanese Unexamined Patent Publication No. 5-270860 (U.S. Pat. No. 5,633,090) or the like with respect to Pb, it is required to reduce Pb to a level suitable to serve as a countermeasure against environmental problems, even in a general electronic, part such as a semiconductor integrated circuit device or the like and a mounting board.
Conventionally, in order to reduce Pb, the countermeasure is performed by replacing the Sn—Pb solder employed in the outer plating step by the another solder (alloy) which does not contain Pb as a main metal, that is, a Pb-free alternate solder (a solder composed of a Pb-free metal) The Pb-free alternate solder is required to have a range of melting temperature similar to that of Sn—Pb and an excellent bonding property, particularly a wetting property. No composition completely satisfying the requirements presently exists, and the solders are selectively used in correspondence with members such as printed circuit boards, the chip part, semiconductor packages and the like. Accordingly, various compositions have been proposed in a Sn-base alloy in correspondence with various usages, for example, an invention in which a Sn—Bi system is employed in place of the Sn—Pb system for the metal employed for the solder layer attached to and formed in the conventional lead, in Japanese Unexamined Patent Publication No. 10-93004 (prior art 1). Further, with respect to the structure of the metal composition of the solder, an invention is proposed in which the package outer lead and the substrate are mounted by using a Sn—Ag—Bi system solder, in Japanese Unexamined Patent Publication No. 11-179586 (WO 99 30866) (prior art 2).
In the case of employing a Sn—Pb eutectic alternate Pb-free solder for the outer plating, the Sn-base alloy is selected at every usage in the same manner as that mentioned in the prior art. However, in particular, in parts mounted on the vehicle, significantly developed mobile electronic devices and parts with high reliability, an alloy excellent in a bonding strength and possessing a heat resisting fatigue property is desired. A Sn—Ag system alloy is known as a Sn-base alloy in the case of attaching great importance to an excellent bonding strength, an excellent heat resisting fatigue property, and a high reliability. The melting point of the Sn—Pb eutectic solder is generally 183° C. On the contrary, the melting point of most of the Sn—Ag system alloy is 200° C. or more, and, as such, is higher than the melting point of the Sn—Pb eutectic solder. Accordingly, it is unavoidable that the reflow temperature at a time of mounting the semiconductor integrated circuit using the Sn—Pb eutectic alternate Pb-free solder becomes high in present system. The inventors of the present application mounted the semiconductor integrated circuit device, on which the inner lead is Ag-plated and the outer lead is plated by using the Pb-free alternate solder having a melting point higher than that of the Sn—Pb eutectic solder, at a reflow temperature higher than in the conventional case and evaluated the product. As a result, the inventors ascertain that product inferiority is generated due to the wire disconnection.